Processing issues in top–down approaches to quantum computer development in silicon

We describe critical processing issues in our development of single-atom devices for solid-state quantum information processing. Integration of single 31P atoms with control gates and single electron transistor (SET) readout structures is addressed in a silicon-based approach. Results on electrical...

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Published inMicroelectronic engineering Vol. 73; pp. 695 - 700
Main Authors Park, S.-J., Persaud, A., Liddle, J.A., Nilsson, J., Bokor, J., Schneider, D.H., Rangelow, I.W., Schenkel, T.
Format Journal Article
LanguageEnglish
Published Elsevier B.V 01.06.2004
Subjects
Electron-beam lithography
Ion implantation
Quantum computer
Qubit
Ion implantation
Qubit
Quantum computer
Electron-beam lithography
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Summary:We describe critical processing issues in our development of single-atom devices for solid-state quantum information processing. Integration of single 31P atoms with control gates and single electron transistor (SET) readout structures is addressed in a silicon-based approach. Results on electrical activation of low-energy (15 keV) P implants in silicon show a strong dose effect on the electrical activation fractions. We identify dopant segregation to the SiO 2/Si interface during rapid thermal annealing as a dopant loss mechanism and discuss means to minimize it. Silicon nanowire SET pairs with nanowire width of 10–20 nm are formed by electron-beam lithography in SOI. We present initial results from Coulomb blockade experiments and discuss issues of control gate integration for sub-40 nm gate pitches.
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ISSN:0167-9317
1873-5568
DOI:10.1016/j.mee.2004.03.037