Performance and Scalability of Strain Engineered 2D MoTe2 Phase-Change Memristors

• Published in: IEEE journal of the Electron Devices Society Vol. 13; pp. 343 - 349
• Main Authors: Guimaraes Leal, Maria Vitoria, Azizimanesh, Ahmad, Hasan, Nazmul, Wu, Stephen M.
• Format: Journal Article
• Language: English
• Published: IEEE 2025
• Subjects: device fabrication; Force; Geometry; Memristor; Memristors; Metals; Optical switches; Performance evaluation; phase-change memory; Strain; strain engineering; Stress; Substrates; two-dimensional materials; Voltage
• ISSN: 2168-6734
• DOI: 10.1109/JEDS.2025.3556316

This work presents a performance optimization and scalability study of a two-dimensional vertical molybdenum ditelluride (MoTe2) phase-change memristor. The device switches between the semimetallic (1T') and semiconducting (2H) states under an electric field. Process-induced strain engineering techniques at the contacts reduces the switching energy barrier, biasing the active region closer to the phase switching point. This work focuses on optimizing this technique to achieve the best yield and device performance, with a low switching voltage (<inline-formula> <tex-math notation="LaTeX">\leq 0.5 </tex-math></inline-formula>V) and high on/off ratio <inline-formula> <tex-math notation="LaTeX">\geq 10{^{{5}}} </tex-math></inline-formula>. Small length and area of the contact between the metal stressor and the 2D 1T'-MoTe2 flake are critical for high yield and performance, potentially due to lowered chances of encountering defects introduced during the fabrication process (L<inline-formula> <tex-math notation="LaTeX">\leq 0.6\mu </tex-math></inline-formula>m and A<inline-formula> <tex-math notation="LaTeX">\leq 0.3\mu </tex-math></inline-formula>m2). Smaller flake contact perimeters <inline-formula> <tex-math notation="LaTeX">\leq 1.2\mu </tex-math></inline-formula>m also reduce defect incidence, and increases on/off ratios. The switching voltage is influenced by the contact-flake geometry, exhibiting a lower value for 2D flake geometries with contact angles <inline-formula> <tex-math notation="LaTeX">\leq 65{^{\text {o}}} </tex-math></inline-formula> likely due to geometric variation in strain distribution effects from process-induced strain engineering. These results demonstrate that by accounting for device geometry, our process may achieve yield approaching 90% with consistent low switching voltage and high on/off ratio. Yield and performance properties become better when scaled down in size due to our phase-change mechanism, which is the opposite behavior to most conductive filament based memristors.