Timing violations due to VDD/VSS bounce

The effect of power supply noise in on-chip power grids and its implications on the path delay in digital circuits is examined. The simulation results show that IR-Drop and the resulting path delay are strongly affected by the layout of the circuit. Power grid design measures to reduce IR-Drop, as w...

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Bibliographic Details
Published inAdvances in radio science Vol. 4; pp. 197 - 205
Main Authors Eireiner, M, Henzler, S, Berthold, J, Pacha, C, Georgakos, G, Schmitt-Landsiedel, D
Format Journal Article
LanguageEnglish
German
Published Katlenburg-Lindau Copernicus GmbH 01.01.2006
Copernicus Publications
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Summary:The effect of power supply noise in on-chip power grids and its implications on the path delay in digital circuits is examined. The simulation results show that IR-Drop and the resulting path delay are strongly affected by the layout of the circuit. Power grid design measures to reduce IR-Drop, as well as their area and performance implications are discussed.
ISSN:1684-9965
1684-9973
DOI:10.5194/ars-4-197-2006