Ultra-small Hysteresis IGZO Thin-Film Transistors with Room-Temperature Sputtered SiO2 as Dielectric Layer

• Published in: Journal of Applied Science and Engineering Vol. 28; no. 10; pp. 1987 - 1993
• Main Authors: Fangfei Han, Zheng Lu, Luan Fu, Lulu Du, Xiaohui Shi
• Format: Journal Article
• Language: English
• Published: Tamkang University Press 01.03.2025
• Subjects: hysteresis; indium gallium zinc oxide (igzo); sputtered sio2; thin-film transistors (tfts)
• ISSN: 2708-9967; 2708-9975
• DOI: 10.6180/jase.202510_28(10).0011

A sputtered silicon dioxide dielectric is prepared for fabrication of indium gallium zinc oxide (IGZO) thin-film transistors (TFTs). We analyzed the dependence of device characteristics on gate voltage range. Clockwise hysteresis occurs at a low gate voltage ( Vgs ≤ 3 V) due to oxide traps near the SiO2/IGZO interface. At higher gate voltage ( Vgs = 5 V) a second, hysteresis collapse appears, which can be attributed to the coexistence of electron trapping and ion migration with a compatible and the opposite contributions to the hysteresis. Due to the dominant ion migration, hysteresis inversion (clockwise to anti-clockwise) appears at Vgs = 7 V. At Vgs = 10 V, devices performance degrades significantly, which may be ascribed to the electrochemical reaction. Further, a bias stress measurement indicates that the devices work effectively under a wide range Vgs of 1 ∼ 7 V