A Review on Design and Verification of Programmable UART with AXI

• Published in: International Journal For Multidisciplinary Research Vol. 6; no. 3
• Main Authors: -, Abhishek R Bharadwaj, -, Tanish Raj K S, -, Vinutha G, -, Jagadeesh Basavaiah
• Format: Journal Article
• Language: English
• Published: 11.05.2024
• ISSN: 2582-2160; 2582-2160
• DOI: 10.36948/ijfmr.2024.v06i03.19860

The evolution of System-on-Chip (SoC) architectures has necessitated the integration of robust communication protocols to ensure efficient and reliable data transfer. Among these, the Universal Asynchronous Receiver/Transmitter (UART) plays a pivotal role in serial communication, particularly when interfaced with the Advanced Extensible Interface (AXI) for high-speed data transactions. This review paper delves into the design intricacies and verification challenges of programmable UARTs within SoC environments, leveraging the AXI protocol. We explore various design methodologies that cater to the low-latency and high-throughput demands of modern SoCs, examining the implementation of UART circuits based on the AMBA bus protocol and their alignment with AXI standards. Furthermore, the paper scrutinizes the verification processes, highlighting the use of SystemVerilog and Universal Verification Methodology (UVM) to ensure the reliability and performance of UART designs. This paper endeavours to offer a consolidated perspective on the present state-of-the-art in UART design and verification by conducting a thorough examination of existing literature and case studies. Additionally, it aims to shed light on potential future advancements and directions for improvement within this domain.