APA (7th ed.) Citation

Rajeswari, P., & Sasi, S. (2025). An optimized simulated annealing memetic algorithm for power and wirelength minimization in VLSI circuit partitioning. International journal of reconfigurable and embedded systems, 14(2), 365. https://doi.org/10.11591/ijres.v14.i2.pp365-374

Chicago Style (17th ed.) Citation

Rajeswari, P., and Smitha Sasi. "An Optimized Simulated Annealing Memetic Algorithm for Power and Wirelength Minimization in VLSI Circuit Partitioning." International Journal of Reconfigurable and Embedded Systems 14, no. 2 (2025): 365. https://doi.org/10.11591/ijres.v14.i2.pp365-374.

MLA (9th ed.) Citation

Rajeswari, P., and Smitha Sasi. "An Optimized Simulated Annealing Memetic Algorithm for Power and Wirelength Minimization in VLSI Circuit Partitioning." International Journal of Reconfigurable and Embedded Systems, vol. 14, no. 2, 2025, p. 365, https://doi.org/10.11591/ijres.v14.i2.pp365-374.