An optimized simulated annealing memetic algorithm for power and wirelength minimization in VLSI circuit partitioning

• Published in: International journal of reconfigurable and embedded systems Vol. 14; no. 2; p. 365
• Main Authors: Rajeswari, P., Sasi, Smitha
• Format: Journal Article
• Language: English
• Published: 01.07.2025
• ISSN: 2089-4864; 2722-2608
• DOI: 10.11591/ijres.v14.i2.pp365-374

The development of physical architecture standards for very large scale integration (VLSI) single and multichip platforms is still in its early stages. To deal with the growing complexity of modern VLSI systems, it has become common practice to split large circuit architectures into smaller, easier-to-manage sub-circuits. Circuit partitioning improves parallel modeling, testing, and system performance by lowering chip size, number of components and interconnects, wire length (WL), and delays. VLSI partitioning's primary goal is to split a circuit into smaller blocks with as few connections as possible between them. This is frequently accomplished by recursive bi-partitioning until the required complexity level is reached. Thus, partitioning is a fundamental circuit design challenge. An efficient remedy that offers a heuristic method that explores the design space to iteratively enhance outcomes is evolutionary computation. In order to minimize WL, area, and interconnections, we provide an optimized simulated annealing memetic algorithm (OSAMA) that combines local search methods with evolutionary tactics. The efficiency of the method was evaluated using criteria like runtime, cost, delay, area, and WL. OSAMA's ability for effective partitioning is demonstrated by experimental results, which confirm that it dramatically lowers important design parameters in VLSI circuits.