Orthogonal Signal based Single Phase FLL with Minimum Computational Overhead for Adverse Grid Conditions

• Published in: IEEE journal of emerging and selected topics in industrial electronics (Print) Vol. 4; no. 4; pp. 1 - 11
• Main Authors: Satyanarayana, Muddasani, Teja, A. V. Ravi
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.10.2023; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Band-pass filters; dc offset; Dynamic response; Estimates; Field programmable gate arrays (FPGA); Filtering algorithms; Frequency estimation; Frequency locked loops; Frequency locking; Gird harmonics; Grid Synchronization; Hardware; Harmonic analysis; Harmonics; Low-pass filters; Modified second order generalized integrator; Power harmonic filters; Single phase grid systems
• ISSN: 2687-9735; 2687-9743
• DOI: 10.1109/JESTIE.2023.3299193

In this paper, a frequency locked loop (FLL) is proposed for distorted single phase grid systems. The proposed algorithm estimates the grid phase and frequency angle with minimal errors by using the orthogonal signal of Harmonic Flag-Modified second-order generalized integrator (HF-MoSOGI) and digital estimator stage. The proposed method achieves these estimates independently without using trigonometric and division operations. The implementation of the proposed FLL is straightforward and has minimum computational overhead. The proposed algorithm, along with the detailed procedure for hardware implementation, is explained in this paper. The simulation and hardware results are presented at various grid adversities to verify the proposed algorithm's improved dynamic response and effectiveness under steady grid disturbances(harmonics and dc offset). The Proposed FLL is also used to implement the single-phase grid-tied inverter using hysteresis current control, and the results in simulation and hardware are reported.