Layout Design of Row Decoder using Cadence

• Published in: International journal for research in applied science and engineering technology Vol. 10; no. 8; pp. 461 - 468
• Main Authors: B S, Vinayashree, K C, Santhosh Babu
• Format: Journal Article
• Language: English
• Published: 31.08.2022
• ISSN: 2321-9653; 2321-9653
• DOI: 10.22214/ijraset.2022.46214

Logic circuits, data transport circuits, and analogue to digital conversions all frequently employ decoders. For the line decoders, a mixed logic design approach incorporating transmission gate logic, pass transistor logic, and complementary metaloxide semiconductor (CMOS) technology is employed to achieve the desired performance and operation. A unique topology is proposed for the 2 to 4 decoders, which calls for a topology with fourteen transistors to reduce operating power and transistor count and a topology with fifteen transistors to achieve high power and low delay performance. For a total of four new designs, standard and inverting decoders are created for each situation. All of the suggested decoders have a low transistor count in comparison to their traditional CMOS architectures. Last but not least, a number of suggested solutions demonstrate a notable improvement in operating power and propagation latency, exceeding CMOS in virtually all instances