RETRACTED ARTICLE: Implementation of efficient reconfigurable FIR filter with control logic for 5G applications

• Published in: Soft computing (Berlin, Germany) Vol. 25; no. 15; pp. 10509 - 10518
• Main Authors: Raju Kalidindi, S. N., Terlapu, Sudheer Kumar, Krishna, M. Vamshi
• Format: Journal Article
• Language: English
• Published: Berlin/Heidelberg Springer Berlin Heidelberg 01.08.2021
• Subjects: Application of Soft Computing; Artificial Intelligence; Computational Intelligence; Control; Engineering; Mathematical Logic and Foundations; Mechatronics; Robotics; Folded direct form; FIR Filter design; Unfolded direct Form; Distributed arithmetic; Coefficient selection; Multiply and accumulate
• ISSN: 1432-7643; 1433-7479
• DOI: 10.1007/s00500-021-05997-7

Filters are used to achieve frequency selectivity on the spectrum of input signal. Due to the stability of finite impulse response (FIR) filters, they are used in most of the applications. In the conventional FIR filters, the frequency band is fixed and cannot be changed once it is designed. Hence, there is a necessity of an FIR filter with auto-adjustment of band width in modern day communication systems like 5G. The design of FIR filter requires more number of filter coefficients to get the desired bandwidth specification. This results in a large slice for field programmable gate array implementation. Here, it proposed a state machine to select different FIR filters with the designated set of coefficients. Each FIR filter is having different set of coefficients, and based on the frequency of the clock signal, the FIR filter is selected and thereby frequency selectivity can be achieved. The proposed method is to implement reconfigurable FIR (RFIR) filter with control logic for auto-adjustment of frequency selections to achieve better band width requirements. The filter order is initially selected as 4 and presented the simulation results. The order of the filter(n) increased to 24 for verifying the bandwidth selection. The proposed architecture is compared with the existing architecture with 16 bits and 11 taps. The proposed method saves 33.5% of look-up-tables (LUTs) compared to the existing methods. Simulation results presented are verified using Xilinx ISE design suite 14.7. The total number of four-input LUTs utilized are 630 for order(n) of the filter 24. Power consumed by the overall design is 195 mW.