Modeling and Understanding the Compact Performance of h‐BN Dual‐Gated ReS 2 Transistor

• Published in: Advanced functional materials Vol. 31; no. 23
• Main Authors: Lee, Kookjin, Choi, Junhee, Kaczer, Ben, Grill, Alexander, Lee, Jae Woo, Van Beek, Simon, Bury, Erik, Diaz‐Fortuny, Javier, Chasin, Adrian, Lee, Jaewoo, Chun, Jungu, Shin, Dong Hoon, Cho, Hyeran, Lee, Sang Wook, Kim, Gyu‐Tae
• Format: Journal Article
• Language: English
• Published: 01.06.2021
• ISSN: 1616-301X; 1616-3028
• DOI: 10.1002/adfm.202100625

Abstract In this study, high‐performance few‐layered ReS 2 field‐effect transistors (FETs), fabricated with hexagonal boron nitride (h‐BN) as top/bottom dual gate dielectrics, are presented. The performance of h‐BN dual gated ReS 2 FET having a trade‐off of performance parameters is optimized using a compact model from analytical choice maps, which consists of three regions with different electrical characteristics. The bottom h‐BN dielectric has almost no defects and provides a physical distance between the traps in the SiO 2 and the carriers in the ReS 2 channel. Using a compact analyzing model and structural advantages, an excellent and optimized performance is introduced consisting of h‐BN dual‐gated ReS 2 with a high mobility of 46.1 cm 2 V −1 s −1 , a high current on/off ratio of ≈10 6 , a subthreshold swing of 2.7 V dec −1 , and a low effective interface trap density ( N t,eff ) of 7.85 × 10 10 cm −2 eV −1 at a small operating voltage (<3 V). These phenomena are demonstrated through not only a fundamental current–voltage analysis, but also technology computer aided design simulations, time‐dependent current, and low‐frequency noise analysis. In addition, a simple method is introduced to extract the interlayer resistance of ReS 2 channel through Y‐function method as a function of constant top gate bias.