A 13-GHz Analog Fractional-N Sampling PLL With a Calibration-assisted Seamless Loop-switching Technique

This work presents a 13-GHz low-jitter and high figure-of-merit (FoM) fractional-N phase-locked loop (PLL) using a digital-to-time converter (DTC)-based sampling PLL architecture. To achieve ultra-low jitter in fractional-N mode, a DTC gain calibration technique and a reconfigurable dual-core voltag...

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Bibliographic Details
Published inJournal of semiconductor technology and science Vol. 25; no. 3; pp. 292 - 300
Main Authors Kim, Seojin, Kim, Youngsik, Kim, Shinwoong
Format Journal Article
LanguageEnglish
Published 대한전자공학회 30.06.2025
Subjects
전기공학
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Summary:This work presents a 13-GHz low-jitter and high figure-of-merit (FoM) fractional-N phase-locked loop (PLL) using a digital-to-time converter (DTC)-based sampling PLL architecture. To achieve ultra-low jitter in fractional-N mode, a DTC gain calibration technique and a reconfigurable dual-core voltage-controlled oscillator (VCO) are applied, while a novel phase offset calibration technique is adopted to provide smooth loop switching transitions. Post-layout simulation results show an integrated rms jitter of 138.5-fs from 10 kHz to 100 MHz. The PLL consumes 4.12 mW and achieves a FoM of -251 dB, operating at a 1.0-V supply. The PLL core is implemented in a 28-nm CMOS process and occupies 0.47 mm2 . KCI Citation Count: 0
ISSN:1598-1657
2233-4866
DOI:10.5573/JSTS.2025.25.3.292