Analysis of FinFET Based Positive Feedback Symmetric Adiabatic Logic for Performance and Security Characteristics

• Published in: Journal of semiconductor technology and science Vol. 25; no. 4; pp. 384 - 396
• Main Authors: Bhuvana, B P, Prathiba, A, Kanchana Bhaaskaran, V S
• Format: Journal Article
• Language: English
• Published: 대한전자공학회 31.08.2025
• Subjects: 전기공학
• ISSN: 1598-1657; 2233-4866
• DOI: 10.5573/JSTS.2025.25.4.384

Over the past few years, the demand for energy efficient and secure Internet of Things (IoT) devices has surged to a greater extent. Hardware cryptographic modules are being widely employed in IoT devices which are vulnerable to power analysis (PA) attacks. The non-linear multiplicative inverse unit employed in S-box has been majorly identified for purpose of analyzing the susceptibility of cryptographic modules against PA attacks. In this paper, the multiplicative unit of S-Box circuit is designed using positive feedback symmetric adiabatic logic (PFSAL). Energy efficiency of PFSAL is discussed and validated by comparison with the commonly employed adiabatic logic circuits, such as SQAL (secure quasi adiabatic logic), CSSAL (charge sharing symmetric adiabatic logic), FinSAL (FinFET based secure adiabatic logic) and EE-SPFAL (energy efficient symmetric positive feedback adiabatic logic). Further, the security characteristics of PFSAL based multiplicative circuit proves its resilience against PA attacks. Circuits have been designed and simulated using FinFET 32 nm BSIMCMG model files using Cadence®Virtuoso EDA tools. Spice simulations show the proposed PFSAL based circuit is 57%, 59%, and 12% more energy efficient than FinFET based SQAL, CSSAL and FinSAL counterparts. KCI Citation Count: 0