A Lightweight AES-256 Accelerator Design through Processing Order Optimization for Low-cost Hardware Security

In the era of AI and IoT, securing sensitive data is paramount, especially for resource-constrained edge devices. This paper presents a novel lightweight Advanced Encryption Standard (AES)-256 accelerator design that optimizes encryption and decryption processes for low-cost hardware security. By re...

Full description

Saved in:
Bibliographic Details
Published inJournal of semiconductor technology and science Vol. 25; no. 4; pp. 406 - 413
Main Authors Lee, Yuseong, Kang, Jaehak, Lee, Jongmin
Format Journal Article
LanguageEnglish
Published 대한전자공학회 31.08.2025
Subjects
전기공학
Online AccessGet full text

Cover

More Information
Summary:In the era of AI and IoT, securing sensitive data is paramount, especially for resource-constrained edge devices. This paper presents a novel lightweight Advanced Encryption Standard (AES)-256 accelerator design that optimizes encryption and decryption processes for low-cost hardware security. By reordering the processing steps in the AES round function and introducing a pre-processing technique in the key expansion process, the proposed architecture enhances both throughput and resource efficiency. Our work results demonstrate that the proposed architecture achieves a throughput of 42.667 Gbps with an area efficiency of 233.69 Kbps/GE. This makes the proposed design an ideal solution for modern IoT devices, where high-speed secure data processing and hardware efficiency are critical. KCI Citation Count: 0
ISSN:1598-1657
2233-4866
DOI:10.5573/JSTS.2025.25.4.406