Exploring CXL-SSD Challenges on Cache Underutilization

• Published in: Journal of semiconductor technology and science Vol. 25; no. 4; pp. 459 - 467
• Main Authors: Lee, Hoon-Hwi, Kim, Min-Jae, You, Jun-Woo, Jang, Hyung-Jun, Ro, Won-Woo
• Format: Journal Article
• Language: English
• Published: 대한전자공학회 31.08.2025
• Subjects: 전기공학
• ISSN: 1598-1657; 2233-4866
• DOI: 10.5573/JSTS.2025.25.4.459

The CXL interface enhances scalability for memory expansion, which is crucial for the demands of emerging memory-intensive applications. However, mismatches between traditional memory hierarchies and CXLenabled memory, particularly when using SSDs as memory space, present critical issues that have not previously been addressed. This paper investigates the deployment of CXL technology in SSDs and the associated data management challenges that differ from those in traditional memory systems. We explore the potential issues of utilizing SSDs as system memory via CXL interfaces, emphasizing the substantial performance bottlenecks caused by bypassing traditional DRAM caching, which leads to CPU resource contention, unintended adverse effects on DRAM, and inefficiencies in SSD access. Based on our findings, we propose improvements to mitigate such challenges by optimizing memory management strategies and system architecture implementations to leverage CXL-enabled SSDs’ capabilities fully. KCI Citation Count: 0