Biased Poly-gate-separated Schottky Barrier Diode in CMOS

• Published in: Journal of semiconductor technology and science Vol. 25; no. 4; pp. 414 - 419
• Main Authors: Kim, Deokgi, Noh, Jaehyun, Choi, Wooyeol, Shim, Dongha
• Format: Journal Article
• Language: English
• Published: 대한전자공학회 31.08.2025
• Subjects: 전기공학
• ISSN: 1598-1657; 2233-4866
• DOI: 10.5573/JSTS.2025.25.4.414

This paper presents a biased poly-gate-separated Schottky barrier diode (biased PGS-SBD). The polygate of PGS-SBD is biased to improve DC (leakage current) or RF performance (cut-off frequency). The operation principles are analyzed using TCAD simulations. The device is fabricated in a 130-nm CMOS process without any process modification. The DC and RF performances are measured and analyzed. The leakage current is reduced from 2.4 × 10−5 to 2.1 × 10−6 mA/µm2 as the poly-gate voltage decreases from +1.0 V to −1.0 V at the diode voltage of −1 V. The cut-off frequency increases from 0.75 to 1.25 THz as the gate voltage increases from −1.0 V to +1.0 V. The proposed device achieved ∼5X lower leakage current or 34% higher cut-off frequency than that of the floating-gate PGS-SBD by controlling the poly-gate voltage. KCI Citation Count: 0