An efficient implementation architecture for wide-band digital downconversion
TN; The wide-band digital receiving systems require digital downconversion(DDC) with high data rate and short tuning time in order to intercept the narrow-band signals within broad tuning bandwidth. But these requirements can not be met by the commercial DDC. In this paper an efficient implementatio...
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Published in | Journal of electronics (China) Vol. 18; no. 1; pp. 38 - 45 |
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Main Authors | , |
Format | Journal Article |
Language | English |
Published |
University of Electronic Science and Technology of China, Chengdu 610054
01.01.2001
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Subjects | |
Online Access | Get full text |
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Summary: | TN; The wide-band digital receiving systems require digital downconversion(DDC) with high data rate and short tuning time in order to intercept the narrow-band signals within broad tuning bandwidth. But these requirements can not be met by the commercial DDC. In this paper an efficient implementation architecture is presented. It combines the flexibility of DFT tuning with the efficiency of the polyphase filter bank decomposition. By first decimating the data prior to filtering and mixing, this architecture gives a better solution to the mismatch between the lower hardware speed and high data rate. The computer simulations show the feasibility of this processing architecture. |
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ISSN: | 0217-9822 1993-0615 |
DOI: | 10.1007/s11767-001-0006-7 |