(Keynote) Epitaxial Si/SiGe Multi-Stacks: From Stacked Nano-Sheet to Fork-Sheet and CFET Devices

• Published in: ECS transactions Vol. 114; no. 2; pp. 15 - 28
• Main Authors: Loo, Roger, Akula, Anjani, Shimura, Yosuke, Porret, Clement, Rosseel, Erik, Dursap, Thomas, Hikavyy, Andriy Yakovitch, Beggiato, Matteo, Bogdanowicz, Janusz, Merkulov, Alex, Ayyad, Mustafa, Han, Han, Richard, Olivier, Impagnatiello, Andrea, Wang, Dong, Yamamoto, Keisuke, Sipőcz, Tamás, Kerekes, Árpád, Mertens, Hans, Horiguchi, Naoto, Langer, Robert
• Format: Journal Article
• Language: English
• Published: The Electrochemical Society, Inc 27.09.2024
• ISSN: 1938-5862; 1938-6737
• DOI: 10.1149/11402.0015ecst

After a short description of the evolution of metal-oxide-semiconductor (MOS) device architectures and the corresponding requirements on epitaxial growth processes, the manuscript describes the material properties of complicated Si/SiGe multi-layer stacks used for complementary field effect transistor (CFET) devices. They contain two different Ge concentrations and have been grown using conventional process gases. A relatively high growth temperature is used to obtain acceptable Si and SiGe growth rates. Still island growth has been suppressed for Ge concentrations up to 40%. Excellent structural and optical material properties of the Si/SiGe multi-layer stack will be reported, with up to 3 + 3 Si channels in the top and bottom part of the stack, respectively. The absence/presence of lattice defects has been verified by room temperature photoluminescence measurements. Photoluminescence measurements at low temperatures are used to study band-to-band luminescence from individual sub-layers and to illustrate the optical material quality of the CFET stack.