Study on Low-jitter and Low-power PLL Architectures for Mobile Audio Systems
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| Published in | Journal of semiconductor technology and science Vol. 22; no. 6; pp. 482 - 492 |
|---|---|
| Main Authors | , , |
| Format | Journal Article |
| Language | English |
| Published |
대한전자공학회
31.12.2022
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| Subjects | |
| Online Access | Get full text |
| ISSN | 1598-1657 2233-4866 |
| DOI | 10.5573/JSTS.2022.22.6.482 |
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| Author | Yujin Kyung Gwang Sub Kim Donghyun Baek |
|---|---|
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| Issue | 6 |
| Keywords | Clock generator low jitter reference-sampling PLL (RSPLL) sub-sampling PLL (SSPLL) phase-locked loop (PLL) phase noise multiplying delay locked loop (MDLL) |
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| StartPage | 482 |
| Title | Study on Low-jitter and Low-power PLL Architectures for Mobile Audio Systems |
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