DSP architecture for cochlear implants

This paper describes low-power DSP architecture for use in cochlear implants. The microsystem, fabricated in TSMC 0.18mum CMOS, consumes 1.79mW from a 1.2V supply and occupies an area of 9.18mm 2 while providing the necessary programmability for high speech comprehension by patients. Standby power c...

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Bibliographic Details
Published in2006 IEEE International Symposium on Circuits and Systems (ISCAS) p. 4 pp.
Main Authors Marsman, E.D., Senger, R.M., Carichner, G.A., Kubba, S., McCorquodale, M.S., Brown, R.B.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2006
Subjects
Band pass filters
Cochlear implants
Computational Intelligence Society
Digital signal processing
Ear
Electrodes
Energy consumption
Hair
Signal processing
Signal processing algorithms
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Summary:This paper describes low-power DSP architecture for use in cochlear implants. The microsystem, fabricated in TSMC 0.18mum CMOS, consumes 1.79mW from a 1.2V supply and occupies an area of 9.18mm 2 while providing the necessary programmability for high speech comprehension by patients. Standby power consumption is 330muW
ISBN:0780393899
9780780393899
ISSN:0271-4302
2158-1525
DOI:10.1109/ISCAS.2006.1692671