A Comprehensive Modeling Framework for Voltage Boosting Bridge in Wireless Charging Applications

The utilization of wireless power transfer in the automotive industry can be proven to be a radical change in the popularization of electric vehicles. This article presents a novel boost full bridge inverter (BFBI) architecture with detailed modeling using extended describing functions comprising sm...

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Bibliographic Details
Published inIEEE journal of emerging and selected topics in industrial electronics (Print) pp. 1 - 11
Main Authors Dabkara, Monika, Prakash P, Saravana, Verma, Arun Kumar
Format Journal Article
LanguageEnglish
Published IEEE 20.08.2025
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ISSN2687-9735
2687-9743
DOI10.1109/JESTIE.2025.3601611

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Summary:The utilization of wireless power transfer in the automotive industry can be proven to be a radical change in the popularization of electric vehicles. This article presents a novel boost full bridge inverter (BFBI) architecture with detailed modeling using extended describing functions comprising small signal and steady-state analysis. The proposed configuration overcomes the drawbacks of conventional voltage, current source inverters, and existing boost topologies for inductive power transfer systems by delivering boosted high-frequency bi-polar ac output voltage, continuous input current with reduced ripple without the need for an additional blocking device. Moreover, a reduced equivalent model for the system is also derived to minimize the modeling complexity. The series-series compensation is engaged with inductive coupling to avoid the bifurcation phenomenon. A fixed frequency control regulates the inverter output current for maximum efficiency and power transfer. Furthermore, detailed operating modes, modeling, and design analysis are derived with boundary conditions to achieve minimum losses in the system are presented. Finally, the theoretical verification is carried out based on MATLAB simulations, and the experimental results are obtained using a laboratory prototype to validate the practicability of the proposed topology. The peak dc-dc efficiency achieved by the hardware is 94.46%, making it prominent among the existing relevant literature at the same power levels.
ISSN:2687-9735
2687-9743
DOI:10.1109/JESTIE.2025.3601611