A 14.5Gb/s word alignment circuit in 0.18μm CMOS technology for high-speed SerDes

This paper presents a word alignment circuit for high speed SerDes system.By using pipeline structure and circuit optimization techniques,the speed of the aligner is increased,and its performance is improved further through adopting the full custom design method.The proposed word aligner has fabrica...

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Bibliographic Details
Published in高技术通讯(英文版) Vol. 20; no. 3; pp. 328 - 332
Main Author 阮伟华 Hu Qingsheng
Format Journal Article
LanguageEnglish
Published Institute of RF-&OE-lCs, Southeast University, Nanjing 210096, P.R.China 2014
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ISSN1006-6748
DOI10.3772/j.issn.1006-6748.2014.03.016

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Summary:This paper presents a word alignment circuit for high speed SerDes system.By using pipeline structure and circuit optimization techniques,the speed of the aligner is increased,and its performance is improved further through adopting the full custom design method.The proposed word aligner has fabricated in 0.18μm CMOS technology with total area of 1.075 × 0.775mm2 including I/O pad.Measurement results show that this circuit achieves the maximum data rate of 14.5Gb/s,while consuming a total power of 34.9mW from a 1.8V supply.
Bibliography:Ruan Weihua , Hu Qingsheng (Institute of RF-&OE-1Cs, Southeast University, Nanjing 210096, P. R. China)
comma detection; word alignment; pipeline; full custom; parallel structure
This paper presents a word alignment circuit for high speed SerDes system.By using pipeline structure and circuit optimization techniques,the speed of the aligner is increased,and its performance is improved further through adopting the full custom design method.The proposed word aligner has fabricated in 0.18μm CMOS technology with total area of 1.075 × 0.775mm2 including I/O pad.Measurement results show that this circuit achieves the maximum data rate of 14.5Gb/s,while consuming a total power of 34.9mW from a 1.8V supply.
11-3683/N
ISSN:1006-6748
DOI:10.3772/j.issn.1006-6748.2014.03.016