一种用于加速度计中的五阶sigma-delta调制器

采用CHRT 0.35 μm CMOS工艺,设计实现了一种用于加速度计中的单环五阶sigma-delta（∑△）调制器.在MATLAB/Simulink下对调制器进行建模,优化参数实现一个稳定的高阶系统,利用根轨迹法分析了系统的稳定性.该电路在250 kHz采样频率、3.3V电压下功耗为3.4 mW.后仿真结果显示,在1 kHz信号带宽下信噪比为108.6 dB,有效位数约为18位,满足了加速度计对后级高精度调制器的要求....

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Bibliographic Details
Published in电子技术应用 Vol. 41; no. 3; pp. 44 - 47
Main Author 程磊 陈中良
Format Journal Article
LanguageChinese
Published 黄淮学院,河南驻马店,463000 2015
Subjects
低通∑△调制器
建模
根轨迹
高阶
根轨迹
modeling
root locus
低通∑△调制器
low-pass ∑△ modulator
high-order
建模
高阶
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Summary:采用CHRT 0.35 μm CMOS工艺,设计实现了一种用于加速度计中的单环五阶sigma-delta（∑△）调制器.在MATLAB/Simulink下对调制器进行建模,优化参数实现一个稳定的高阶系统,利用根轨迹法分析了系统的稳定性.该电路在250 kHz采样频率、3.3V电压下功耗为3.4 mW.后仿真结果显示,在1 kHz信号带宽下信噪比为108.6 dB,有效位数约为18位,满足了加速度计对后级高精度调制器的要求.
Bibliography:Cheng Lei, Chen Zhongliang （Huanghuai University, Zhumadian 463000, China）
11-2305/TN
A single-loop fifth-order sigma-delta（∑△） modulator circuit applied in accelerometer is designed using CHRT 0. 35 μm CMOS process. The modulator is modeled and analyzed in MATLAB/Simulink and parameters are optimized to achieve a stable high-order system. The system stability is analyzed based on the root locus. The power dissipation of the circuit is about 3.4 mW with sampling frequency 250 kHz at a 3.3 V power supply. The post-simulation result indicates that the signal-to-noise -ratio （SNR） is 108.6 dB with 18-bit resolution over a signal bandwidth of 1 kHz, which meets the accelerometer＇s demand for subsequent stage high-precision modulator.
low-pass ∑△ modulator ; modeling; high-order ; root locus
ISSN:0258-7998
DOI:10.16157/j.issn.0258-7998.2015.03.010