正交匹配追踪算法的优化设计与FPGA实现

设计了一种基于FPGA的正交匹配追踪(Orthogonal Matching Pursuit,OMP)算法的硬件优化结构,对OMP算法进行了改进,大大减少了乘法运算次数;在矩阵分解部分采用了交替柯列斯基分解(Alternative Cholesky Decomposition,ACD)方法避免开方运算,以减小计算延迟,整个系统采用并行计算、资源复用技术,在提高运算速度的同时减少资源利用.在Quartus Ⅱ开发环境下对该设计进行了RTL级描述,在Altera公司的Cyclone Ⅱ EP2C70F672C6上进行综合并完成时序仿真,仿真结果验证了设计的正确性....

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Bibliographic Details
Published in电子技术应用 Vol. 40; no. 10; pp. 79 - 82
Main Author 莫禹钧 柏正尧 黄振 董亮 周燕
Format Journal Article
LanguageChinese
Published 中国科学院云南天文台,云南昆明650011 2014
云南大学信息学院,云南昆明,650091%云南大学信息学院,云南昆明650091
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Summary:设计了一种基于FPGA的正交匹配追踪(Orthogonal Matching Pursuit,OMP)算法的硬件优化结构,对OMP算法进行了改进,大大减少了乘法运算次数;在矩阵分解部分采用了交替柯列斯基分解(Alternative Cholesky Decomposition,ACD)方法避免开方运算,以减小计算延迟,整个系统采用并行计算、资源复用技术,在提高运算速度的同时减少资源利用.在Quartus Ⅱ开发环境下对该设计进行了RTL级描述,在Altera公司的Cyclone Ⅱ EP2C70F672C6上进行综合并完成时序仿真,仿真结果验证了设计的正确性.
Bibliography:This paper presents a novel hardware architecture for Orthogonal Matching Pursuit (OMP) algorithm.OMP algorithm is improved to reduce the number of multiplications.Alternative Cholesky Decomposition(ACD) which avoids square root calculations is used in the part of matrix decomposition to decrease computation delay.The parallel implementation and resource multiplexing are utilized to improve computing speed and resource utilization.This design is described by using RTL HDL and implemented with Altera's PFGA Cyclone Ⅱ EP2C70F672C6.The timing simulation is carried under the Quartus Ⅱ.Simulation results verify the correctness of the design.
Mo Yujun,Bai Zhengyao,Huang Zhen,Dong Liang,Zhou Yan( 1.School of Information Science and Engineering,Yunnan University,Kunming 650091 ,China; 2.School of Information Science and Engineering,Yunnan University,Kunming 650091 ,China;Yunnan Observatories, Chinese Academy of Sciences, Kunming 650011, China)
compressed sensing;orthogonal matching pursuit algorithm;alternative Cholesk
ISSN:0258-7998