An ultra-low-power programmable analog bionic ear processor

• Published in: IEEE transactions on biomedical engineering Vol. 52; no. 4; pp. 711 - 727
• Main Authors: Sarpeshkar, R., Salthouse, C., Ji-Jon Sit, Baker, M.W., Zhak, S.M., Lu, T.K.-T., Turicchia, L., Balster, S.
• Format: Journal Article
• Language: English
• Published: United States IEEE 01.04.2005; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Algorithms; Batteries; BiCMOS integrated circuits; Bionic ear; Bionics - instrumentation; cochlear implant; Cochlear Implants; Dynamic range; Ear; Electrets; Electric Power Supplies; Electrodes; Energy consumption; Equipment Design; Equipment Failure Analysis; Gain control; hearing aids; low power; Microcomputers; Microphones; Reproducibility of Results; Sensitivity and Specificity; Signal Processing, Computer-Assisted - instrumentation; Sound Spectrography - instrumentation; spectrum analysis; speech recognition
• ISSN: 0018-9294; 1558-2531
• DOI: 10.1109/TBME.2005.844043

We report a programmable analog bionic ear (cochlear implant) processor in a 1.5-/spl mu/m BiCMOS technology with a power consumption of 211 /spl mu/W and 77-dB dynamic range of operation. The 9.58 mm/spl times/9.23 mm processor chip runs on a 2.8 V supply and has a power consumption that is lower than state-of-the-art analog-to-digital (A/D)-then-DSP designs by a factor of 25. It is suitable for use in fully implanted cochlear-implant systems of the future which require decades of operation on a 100-mAh rechargeable battery with a finite number of charge-discharge cycles. It may also be used as an ultra-low-power spectrum-analysis front end in portable speech-recognition systems. The power consumption of the processor includes the 100 /spl mu/W power consumption of a JFET-buffered electret microphone and an associated on-chip microphone front end. An automatic gain control circuit compresses the 77-dB input dynamic range into a narrower internal dynamic range (IDR) of 57 dB at which each of the 16 spectral channels of the processor operate. The output bits of the processor are scanned and reported off chip in a format suitable for continuous-interleaved-sampling stimulation of electrodes. Power-supply-immune biasing circuits ensure robust operation of the processor in the high-RF-noise environment typical of cochlear implant systems.