Window Memory Layout Scheme for Alternate Row-Wise/Column-Wise Matrix Access

• Published in: IEICE Transactions on Information and Systems Vol. E96.D; no. 12; pp. 2765 - 2775
• Main Authors: GUO, Lei, TANG, Yuhua, DOU, Yong, LEI, Yuanwu, MA, Meng, ZHOU, Jie
• Format: Journal Article
• Language: English; Japanese
• Published: Oxford The Institute of Electronics, Information and Communication Engineers 2013; Oxford University Press
• Subjects: alternate row-wise/column-wise matrix access; Applied sciences; Bandwidth; Central processing units; Circuit properties; Columns (structural); Computer science; control theory; systems; Control system analysis; Control theory. Systems; Digital circuits; Dynamic random access memory; Dynamics; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; Field programmable gate arrays; FPGA; GPU; Integrated circuits; Integrated circuits by function (including memories and processors); Organization, operation and development plans; Platforms; Radiocommunications; SDRAM; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Telecommunications; Telecommunications and information theory; window memory layout scheme (WMLS); window memory layout scheme (WMLS); Chirp; Wireless markup language; Processor; FPGA; Random access memory; Scientific application; Control system; Field programmable gate array; Bandwidth allocation; GPU; Constant modulus algorithm; alternate row-wise/column-wise matrix access; Non volatile memory; Storage management; CMA; Integrated circuit; Resource management; SDRAM; Memory organization; Dynamic random access memory; High rate transmission
• ISSN: 0916-8532; 1745-1361
• DOI: 10.1587/transinf.E96.D.2765

The effective bandwidth of the dynamic random-access memory (DRAM) for the alternate row-wise/column-wise matrix access (AR/CMA) mode, which is a basic characteristic in scientific and engineering applications, is very low. Therefore, we propose the window memory layout scheme (WMLS), which is a matrix layout scheme that does not require transposition, for AR/CMA applications. This scheme maps one row of a logical matrix into a rectangular memory window of the DRAM to balance the bandwidth of the row- and column-wise matrix access and to increase the DRAM IO bandwidth. The optimal window configuration is theoretically analyzed to minimize the total number of no-data-visit operations of the DRAM. Different WMLS implementationsare presented according to the memory structure of field-programmable gata array (FPGA), CPU, and GPU platforms. Experimental results show that the proposed WMLS can significantly improve DRAM bandwidth for AR/CMA applications. achieved speedup factors of 1.6× and 2.0× are achieved for the general-purpose CPU and GPU platforms, respectively. For the FPGA platform, the WMLS DRAM controller is custom. The maximum bandwidth for the AR/CMA mode reaches 5.94 GB/s, which is a 73.6% improvement compared with that of the traditional row-wise access mode. Finally, we apply WMLS scheme for Chirp Scaling SAR application, comparing with the traditional access approach, the maximum speedup factors of 4.73X, 1.33X and 1.56X can be achieved for FPGA, CPU and GPU platform, respectively.