FPGA based system for automatic cDNA microarray image processing

• Published in: Computerized medical imaging and graphics Vol. 36; no. 5; pp. 419 - 429
• Main Authors: Belean, Bogdan, Borda, Monica, Le Gal, Bertrand, Terebes, Romulus
• Format: Journal Article
• Language: English
• Published: United States Elsevier Ltd 01.07.2012; Elsevier
• Subjects: Algorithms; Automated; Automation; Computation; Cost analysis; Engineering Sciences; Field programmable gate arrays; FPGA technology; Gene expression; Hardware; Image Enhancement - methods; Image Interpretation, Computer-Assisted - methods; Image processing; In Situ Hybridization, Fluorescence - methods; Internal Medicine; Micro and nanotechnologies; Microarray; Microelectronics; Microscopy, Fluorescence - methods; Oligonucleotide Array Sequence Analysis - methods; Other; Parallel computation; Pattern Recognition, Automated - methods; Reproducibility of Results; Sensitivity and Specificity; Parallel computation; Image processing; Microarray; Gene expression; FPGA technology
• ISSN: 0895-6111; 1879-0771; 1879-0771
• DOI: 10.1016/j.compmedimag.2012.01.002

Automation is an open subject in DNA microarray image processing, aiming reliable gene expression estimation. The paper presents a novel shock filter based approach for automatic microarray grid alignment. The proposed method brings up significantly reduced computational complexity compared to state of the art approaches, while similar results in terms of accuracy are achieved. Based on this approach, we also propose an FPGA based system for microarray image analysis that eliminates the shortcomings of existing software platforms: user intervention, increased computational time and cost. Our system includes application-specific architectures which involve algorithm parallelization, aiming fast and automated cDNA microarray image processing. The proposed automated image processing chain is implemented both on a general purpose processor and using the developed hardware architectures as co-processors in a FPGA based system. The comparative results included in the last section show that an important gain in terms of computational time is obtained using hardware based implementations.