高性能可重构流水线ADC的设计与仿真

提出了一种14bit、100MS/s可重构流水线ADC的设计方案,在采样/保持电路、栅压自举开关、折叠式共源共栅运算放大器、可重构控制器等关键电路上均有明显改进,降低了非理想因素对系统的影响,保证了所设计的流水线ADC的指标实现,并对关键模块电路和ADC系统进行了仿真验证。...

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Bibliographic Details
Published in电子技术应用 Vol. 39; no. 4; pp. 39 - 41
Main Author 陈振宇 王立志 任晓岳
Format Journal Article
LanguageChinese
Published 空军工程大学理学院,陕西西安,710051 2013
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Summary:提出了一种14bit、100MS/s可重构流水线ADC的设计方案,在采样/保持电路、栅压自举开关、折叠式共源共栅运算放大器、可重构控制器等关键电路上均有明显改进,降低了非理想因素对系统的影响,保证了所设计的流水线ADC的指标实现,并对关键模块电路和ADC系统进行了仿真验证。
Bibliography:A reconfigurable 14 bit and 100 MS/s pipelined ADC is proposed in this paper. To reduce the influence of non-ideal factors and achieve the design objectives, this paper has improved obviously on the design of some key units including sam-piing-and-hold circuit, bootstrapped switch, folded cascade amplifier and reconfigurable controller. The paper also discusses the sim-ulation of the key units and the system.
communication protocols ; reconfigurable pipelined ADC ; bootstrapped switch ; non-ideal factors ; simulation
Chen Zhenyu, Wang Lizhi, Ren Xiaoyue (School of Science, Air Force Engineering University, Xi'an 710051, China)
11-2305/TN
ISSN:0258-7998