Van der Waals negative capacitance transistors

• Published in: Nature communications Vol. 10; no. 1; pp. 3037 - 8
• Main Authors: Wang, Xiaowei, Yu, Peng, Lei, Zhendong, Zhu, Chao, Cao, Xun, Liu, Fucai, You, Lu, Zeng, Qingsheng, Deng, Ya, Zhou, Jiadong, Fu, Qundong, Wang, Junling, Huang, Yizhong, Liu, Zheng
• Format: Journal Article
• Language: English
• Published: England Nature Publishing Group 10.07.2019; Nature Publishing Group UK; Nature Portfolio
• Subjects: Bend radius; Boltzmann distribution; Capacitance; Energy consumption; Field effect transistors; Heterostructures; Molybdenum; Molybdenum disulfide; MOSFETs; Power consumption; Semiconductor devices; Transistors; Voltage gain
• ISSN: 2041-1723; 2041-1723
• DOI: 10.1038/s41467-019-10738-4

The Boltzmann distribution of electrons sets a fundamental barrier to lowering energy consumption in metal-oxide-semiconductor field-effect transistors (MOSFETs). Negative capacitance FET (NC-FET), as an emerging FET architecture, is promising to overcome this thermionic limit and build ultra-low-power consuming electronics. Here, we demonstrate steep-slope NC-FETs based on two-dimensional molybdenum disulfide and CuInP S (CIPS) van der Waals (vdW) heterostructure. The vdW NC-FET provides an average subthreshold swing (SS) less than the Boltzmann's limit for over seven decades of drain current, with a minimum SS of 28 mV dec . Negligible hysteresis is achieved in NC-FETs with the thickness of CIPS less than 20 nm. A voltage gain of 24 is measured for vdW NC-FET logic inverter. Flexible vdW NC-FET is further demonstrated with sub-60 mV dec switching characteristics under the bending radius down to 3.8 mm. These results demonstrate the great potential of vdW NC-FET for ultra-low-power and flexible applications.