III–V compound semiconductor transistors—from planar to nanowire structures

• Published in: MRS bulletin Vol. 39; no. 8; pp. 668 - 677
• Main Authors: Riel, Heike, Wernersson, Lars-Erik, Hong, Minghwei, del Alamo, Jesús A.
• Format: Journal Article
• Language: English
• Published: New York, USA Cambridge University Press 01.08.2014; Springer International Publishing; Springer Nature B.V
• Subjects: Applied and Technical Physics; Characterization and Evaluation of Materials; Devices; Electrical Engineering, Electronic Engineering, Information Engineering; Elektroteknik och elektronik; Energy Materials; Engineering and Technology; Heterostructures; Logic; Materials Engineering; Materials Science; MOSFETs; Nanotechnology; Nanowires; New Materials for Post-Si Computing; Semiconductor devices; Semiconductors; Teknik; Transistors; semiconducting; III-V; devices; electrical properties; compound; microelectronics
• ISSN: 0883-7694; 1938-1425; 1938-1425
• DOI: 10.1557/mrs.2014.137

Conventional silicon transistor scaling is fast approaching its limits. An extension of the logic device roadmap to further improve future performance increases of integrated circuits is required to propel the electronics industry. Attention is turning to III–V compound semiconductors that are well positioned to replace silicon as the base material in logic switching devices. Their outstanding electron transport properties and the possibility to tune heterostructures provide tremendous opportunities to engineer novel nanometer-scale logic transistors. The scaling constraints require an evolution from planar III–V metal oxide semiconductor field-effect transistors (MOSFETs) toward transistor channels with a three-dimensional structure, such as nanowire FETs, to achieve future performance needs for complementary metal oxide semiconductor (CMOS) nodes beyond 10 nm. Further device innovations are required to increase energy efficiency. This could be addressed by tunnel FETs (TFETs), which rely on interband tunneling and thus require advanced III–V heterostructures for optimized performance. This article describes the challenges and recent progress toward the development of III–V MOSFETs and heterostructure TFETs—from planar to nanowire devices—integrated on a silicon platform to make these technologies suitable for future CMOS applications.