A Field-Programmable Gate Array-Based Adaptive Sleep Posture Analysis Accelerator for Real-Time Monitoring

• Published in: Sensors (Basel, Switzerland) Vol. 24; no. 22; p. 7104
• Main Authors: Sravanthi, Mangali, Gunturi, Sravan Kumar, Chinnaiah, Mangali Chinna, Lam, Siew-Kei, Divya Vani, G., Basha, Mudasar, Janardhan, Narambhatla, Hari Krishna, Dodde, Dubey, Sanjay
• Format: Journal Article
• Language: English
• Published: Switzerland MDPI AG 01.11.2024; MDPI
• Subjects: Accelerometry - instrumentation; adaptive posture analysis; Algorithms; Data processing; Design and construction; Digital integrated circuits; Edge computing; Field programmable gate arrays; FPGA; Health aspects; Humans; Learning; Medical research; Methods; Monitoring, Physiologic - instrumentation; Monitoring, Physiologic - methods; Posture; Posture - physiology; sensor fusion; Sensors; Sleep; Sleep - physiology; Sleep disorders; sleep posture recognition; India; sensor fusion; adaptive posture analysis; FPGA; sleep posture recognition
• ISSN: 1424-8220; 1424-8220
• DOI: 10.3390/s24227104

This research presents a sleep posture monitoring system designed to assist the elderly and patient attendees. Monitoring sleep posture in real time is challenging, and this approach introduces hardware-based edge computation methods. Initially, we detected the postures using minimally optimized sensing modules and fusion techniques. This was achieved based on subject (human) data at standard and adaptive levels using posture-learning processing elements (PEs). Intermittent posture evaluation was performed with respect to static and adaptive PEs. The final stage was accomplished using the learned subject posture data versus the real-time posture data using posture classification. An FPGA-based Hierarchical Binary Classifier (HBC) algorithm was developed to learn and evaluate sleep posture in real time. The IoT and display devices were used to communicate the monitored posture to attendant/support services. Posture learning and analysis were developed using customized, reconfigurable VLSI architectures for sensor fusion, control, and communication modules in static and adaptive scenarios. The proposed algorithms were coded in Verilog HDL, simulated, and synthesized using VIVADO 2017.3. A Zed Board-based field-programmable gate array (FPGA) Xilinx board was used for experimental validation.