A Self-Aligned a-IGZO Thin-Film Transistor Using a New Two-Photo-Mask Process with a Continuous Etching Scheme

• Published in: Materials Vol. 7; no. 8; pp. 5761 - 5768
• Main Authors: Fan, Ching-Lin, Shang, Ming-Chi, Li, Bo-Jyun, Lin, Yu-Zuo, Wang, Shea-Jue, Lee, Win-Der
• Format: Journal Article
• Language: English
• Published: Switzerland MDPI AG 11.08.2014; MDPI
• Subjects: amorphous indium–gallium–zinc–oxide (a-IGZO); back-side exposure; backside-lift-off (BLO); Capacitance; Delay; Drains; Electrodes; Engineering; Etching; Glass substrates; self-aligned process; Semiconductor devices; Semiconductors; Silicon; Thin film transistors; thin-film transistor (TFT); Transistors; two-photo-mask process; Taiwan; backside-lift-off (BLO); back-side exposure; self-aligned process; thin-film transistor (TFT); amorphous indium–gallium–zinc–oxide (a-IGZO); two-photo-mask process
• ISSN: 1996-1944; 1996-1944
• DOI: 10.3390/ma7085761

Minimizing the parasitic capacitance and the number of photo-masks can improve operational speed and reduce fabrication costs. Therefore, in this study, a new two-photo-mask process is proposed that exhibits a self-aligned structure without an etching-stop layer. Combining the backside-ultraviolet (BUV) exposure and backside-lift-off (BLO) schemes can not only prevent the damage when etching the source/drain (S/D) electrodes but also reduce the number of photo-masks required during fabrication and minimize the parasitic capacitance with the decreasing of gate overlap length at same time. Compared with traditional fabrication processes, the proposed process yields that thin-film transistors (TFTs) exhibit comparable field-effect mobility (9.5 cm²/V·s), threshold voltage (3.39 V), and subthreshold swing (0.3 V/decade). The delay time of an inverter fabricated using the proposed process was considerably decreased.