List Scheduling in Embedded Systems Under Memory Constraints

Video decoding and image processing in embedded systems are subject to strong resource constraints, particularly in terms of memory. List-scheduling heuristics with static priorities (HEFT, SDC, etc.) being the oft-cited solutions due to both their good performance and their low complexity, we propo...

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Bibliographic Details
Published inInternational journal of parallel programming Vol. 43; no. 6; pp. 1103 - 1128
Main Authors Arras, Paul-Antoine, Fuin, Didier, Jeannot, Emmanuel, Stoutchinin, Arthur, Thibault, Samuel
Format Journal Article
LanguageEnglish
Published New York Springer US 01.12.2015
Springer Nature B.V
Springer Verlag
Subjects
Algorithms
Computer programming
Computer Science
Decoding
Distributed, Parallel, and Cluster Computing
Dynamic tests
Embedded Systems
Footprints
Graphs
Heuristic
Image processing
Parallel processing
Priorities
Processor Architectures
Scheduling
Software
Software Engineering/Programming and Operating Systems
Studies
Tasks
Theory of Computation
Task graphs
Scheduling
Video decoding
System on chip
Memory
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Summary:Video decoding and image processing in embedded systems are subject to strong resource constraints, particularly in terms of memory. List-scheduling heuristics with static priorities (HEFT, SDC, etc.) being the oft-cited solutions due to both their good performance and their low complexity, we propose a method aimed at introducing the notion of memory into them. Moreover, we show that through adequate adjustment of task priorities and judicious resort to insertion-based policy, speedups up to 20 % can be achieved. We also show that our technique allows to prevent deadlock and to substantially reduce the required memory footprint compared to classic list-scheduling heuristics. Lastly, we propose a methodology to assess the appropriateness of dynamic scheduling in this context.
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ISSN:0885-7458
1573-7640
DOI:10.1007/s10766-014-0338-1