Energy-Efficient GHz-Class Charge-Recovery Logic
In this paper, we present Boost Logic, a charge- recovery circuit family that can operate efficiently at clock frequencies in excess of 1 GHz. To achieve high energy efficiency, Boost Logic relies on a combination of aggressive voltage scaling, gate overdrive, and charge-recovery techniques. In post...
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Published in | IEEE journal of solid-state circuits Vol. 42; no. 1; pp. 38 - 47 |
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Main Authors | , , |
Format | Journal Article Conference Proceeding |
Language | English |
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New York, NY
IEEE
01.01.2007
Institute of Electrical and Electronics Engineers The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
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Abstract | In this paper, we present Boost Logic, a charge- recovery circuit family that can operate efficiently at clock frequencies in excess of 1 GHz. To achieve high energy efficiency, Boost Logic relies on a combination of aggressive voltage scaling, gate overdrive, and charge-recovery techniques. In post-layout simulations of 16-bit multipliers with a 0.13-mum CMOS process at 1GHz, a Boost Logic implementation achieves 5 times higher energy efficiency than its minimum-energy pipelined, voltage-scaled, static CMOS counterpart at the expense of 3 times longer latency. In a fully integrated test chip implemented using a 0.13-mum bulk silicon process and on-chip inductors, chains of Boost Logic gates operate at clock frequencies up to 1.3 GHz with a 1.5-V supply. When resonating at 850 MHz with a 1.2-V supply, the Boost Logic test chip achieves 60% charge-recovery |
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AbstractList | In this paper, we present Boost Logic, a charge- recovery circuit family that can operate efficiently at clock frequencies in excess of 1 GHz. To achieve high energy efficiency, Boost Logic relies on a combination of aggressive voltage scaling, gate overdrive, and charge-recovery techniques. In post-layout simulations of 16-bit multipliers with a 0.13-mum CMOS process at 1GHz, a Boost Logic implementation achieves 5 times higher energy efficiency than its minimum-energy pipelined, voltage-scaled, static CMOS counterpart at the expense of 3 times longer latency. In a fully integrated test chip implemented using a 0.13-mum bulk silicon process and on-chip inductors, chains of Boost Logic gates operate at clock frequencies up to 1.3 GHz with a 1.5-V supply. When resonating at 850 MHz with a 1.2-V supply, the Boost Logic test chip achieves 60% charge-recovery In this paper, we present Boost Logic, a charge- recovery circuit family that can operate efficiently at clock frequencies in excess of 1 GHz. To achieve high energy efficiency, Boost Logic relies on a combination of aggressive voltage scaling, [abstract truncated by publisher]. |
Author | Chueh, J.-Y. Sathe, V.S. Papaefthymiou, M.C. |
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Keywords | Arithmetic circuit Gate voltage Adiabatic Logic gate Energy recovery Clock Inductor Implementation Pipeline processing Logic circuit resonant systems Low voltage Power consumption Integrated circuit testing Energetic efficiency Complementary MOS technology charge-recovery Integrated circuit Multiplier Built in self test |
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References | ref13 svilan (ref14) 2000 ref10 younis (ref1) 1993 ref2 ziesler (ref5) 2003 ref8 (ref12) 1985 ref7 maksimovic (ref4) 1997 ref9 sathe (ref11) 2006 ref3 ref6 |
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SubjectTerms | Adiabatic Applied sciences charge-recovery Chips Circuit properties Circuit simulation Circuits Clocks CMOS CMOS logic circuits CMOS process Delay Design. Technologies. Operation analysis. Testing Digital circuits Electric potential Electric, optical and optoelectronic circuits Electronic circuits Electronics Energy efficiency energy recovery Exact sciences and technology Frequency Gates (circuits) Integrated circuits Integrated circuits by function (including memories and processors) Logic Logic circuits Logic testing resonant systems Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Testing, measurement, noise and reliability Voltage |
Title | Energy-Efficient GHz-Class Charge-Recovery Logic |
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