Energy-Efficient GHz-Class Charge-Recovery Logic

• Published in: IEEE journal of solid-state circuits Vol. 42; no. 1; pp. 38 - 47
• Main Authors: Sathe, V.S., Chueh, J.-Y., Papaefthymiou, M.C.
• Format: Journal Article Conference Proceeding
• Language: English
• Published: New York, NY IEEE 01.01.2007; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Adiabatic; Applied sciences; charge-recovery; Chips; Circuit properties; Circuit simulation; Circuits; Clocks; CMOS; CMOS logic circuits; CMOS process; Delay; Design. Technologies. Operation analysis. Testing; Digital circuits; Electric potential; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Energy efficiency; energy recovery; Exact sciences and technology; Frequency; Gates (circuits); Integrated circuits; Integrated circuits by function (including memories and processors); Logic; Logic circuits; Logic testing; resonant systems; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Testing, measurement, noise and reliability; Voltage; Arithmetic circuit; Gate voltage; Adiabatic; Logic gate; Energy recovery; Clock; Inductor; Implementation; Pipeline processing; Logic circuit; resonant systems; Low voltage; Power consumption; Integrated circuit testing; Energetic efficiency; Complementary MOS technology; charge-recovery; Integrated circuit; Multiplier; Built in self test
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2006.885053

In this paper, we present Boost Logic, a charge- recovery circuit family that can operate efficiently at clock frequencies in excess of 1 GHz. To achieve high energy efficiency, Boost Logic relies on a combination of aggressive voltage scaling, gate overdrive, and charge-recovery techniques. In post-layout simulations of 16-bit multipliers with a 0.13-mum CMOS process at 1GHz, a Boost Logic implementation achieves 5 times higher energy efficiency than its minimum-energy pipelined, voltage-scaled, static CMOS counterpart at the expense of 3 times longer latency. In a fully integrated test chip implemented using a 0.13-mum bulk silicon process and on-chip inductors, chains of Boost Logic gates operate at clock frequencies up to 1.3 GHz with a 1.5-V supply. When resonating at 850 MHz with a 1.2-V supply, the Boost Logic test chip achieves 60% charge-recovery