Application of high pressure deuterium annealing for improving the hot carrier reliability of CMOS transistors

• Published in: IEEE electron device letters Vol. 21; no. 5; pp. 221 - 223
• Main Authors: Jinju Lee, Kangguo Cheng, Zhi Chen, Hess, K., Lyding, J.W., Young-Kwang Kim, Hyui-Seung Lee, Young-Wug Kim, Kwang-Pyuk Suh
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.05.2000; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: ANNEALING; CARRIER LIFETIME; Carriers; CHARGE CARRIERS; CMOS; CMOS technology; DEUTERIUM; Electric variables; ENGINEERING; Hot carriers; Hydrogen; Mass spectroscopy; Metallization; MOS TRANSISTORS; RELIABILITY; Semiconductor devices; Silicon oxynitride; Stress; Testing; Transistors; Wafers
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/55.841302

We present the effect of high pressure deuterium annealing on hot carrier reliability improvements of CMOS transistors. High pressure annealing increases the rate of deuterium incorporation at the SiO/sub 2//Si interface. We have achieved a significant lifetime improvement (90/spl times/) from fully processed wafers (four metal layers) with nitride sidewall spacers and SiON cap layers. The improvement was determined by comparing to wafers that were annealed in a conventional hydrogen forming gas anneal. The annealing time to achieve the same level of improvement is also significantly reduced. The increased incorporation of D at high pressure was confirmed by the secondary ion mass spectrometry characterization.