High-Current-Density Vertical-Tunneling Transistors from Graphene/Highly Doped Silicon Heterostructures

Scalable fabrication of vertical‐tunneling transistors is presented based on heterostructures formed between graphene, highly doped silicon, and its native oxide. Benefiting from the large density of states of highly doped silicon, the tunneling transistors can deliver a current density over 20 A cm...

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Published inAdvanced materials (Weinheim) Vol. 28; no. 21; pp. 4120 - 4125
Main Authors Liu, Yuan, Sheng, Jiming, Wu, Hao, He, Qiyuan, Cheng, Hung-Chieh, Shakir, Muhammad Imran, Huang, Yu, Duan, Xiangfeng
Format Journal Article
LanguageEnglish
Published Germany Blackwell Publishing Ltd 01.06.2016
Subjects
Carrier transport
Current density
Graphene
graphene-silicon junctions
Heterostructures
high current density
Oxides
Semiconductor devices
Silicon
Transistors
tunneling transistors
vertical transistors
vertical transistors
high current density
tunneling transistors
graphene-silicon junctions
graphene
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Summary:Scalable fabrication of vertical‐tunneling transistors is presented based on heterostructures formed between graphene, highly doped silicon, and its native oxide. Benefiting from the large density of states of highly doped silicon, the tunneling transistors can deliver a current density over 20 A cm−2. This study demonstrates that the interfacial native oxide plays a crucial role in governing the carrier transport in graphene–silicon heterostructures.
Bibliography:istex:68A0355E98FE878DC828BBEF8C30ECC23C3519EC
ONR - No. N00014-15-1-2368
ark:/67375/WNG-7FJF52SN-S
ArticleID:ADMA201506173
ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 23
ISSN:0935-9648
1521-4095
DOI:10.1002/adma.201506173