Wafer-scale functional circuits based on two dimensional semiconductors with fabrication optimized by machine learning

• Published in: Nature communications Vol. 12; no. 1; p. 5953
• Main Authors: Chen, Xinyu, Xie, Yufeng, Sheng, Yaochen, Tang, Hongwei, Wang, Zeming, Wang, Yu, Wang, Yin, Liao, Fuyou, Ma, Jingyi, Guo, Xiaojiao, Tong, Ling, Liu, Hanqi, Liu, Hao, Wu, Tianxiang, Cao, Jiaxin, Bu, Sitong, Shen, Hui, Bai, Fuyu, Huang, Daming, Deng, Jianan, Riaud, Antoine, Xu, Zihan, Wu, Chenjian, Xing, Shiwei, Lu, Ye, Ma, Shunli, Sun, Zhengzong, Xue, Zhongyin, Di, Zengfeng, Gong, Xiao, Zhang, David Wei, Zhou, Peng, Wan, Jing, Bao, Wenzhong
• Format: Journal Article
• Language: English
• Published: London Nature Publishing Group UK 12.10.2021; Nature Publishing Group; Nature Portfolio
• Subjects: 142/126; 639/166/987; 639/301/357/1018; 639/925/927/1007; Algorithms; Analog circuits; Circuits; Design standards; Electronic materials; Electronics industry; Fabrication; Field effect transistors; Functional morphology; Graphene; Humanities and Social Sciences; Layered materials; Learning algorithms; Machine learning; Molybdenum disulfide; multidisciplinary; Optimization; Process parameters; Science; Science (multidisciplinary); Semiconductor devices; Semiconductors; Threshold voltage
• ISSN: 2041-1723; 2041-1723
• DOI: 10.1038/s41467-021-26230-x

Triggered by the pioneering research on graphene, the family of two-dimensional layered materials (2DLMs) has been investigated for more than a decade, and appealing functionalities have been demonstrated. However, there are still challenges inhibiting high-quality growth and circuit-level integration, and results from previous studies are still far from complying with industrial standards. Here, we overcome these challenges by utilizing machine-learning (ML) algorithms to evaluate key process parameters that impact the electrical characteristics of MoS 2 top-gated field-effect transistors (FETs). The wafer-scale fabrication processes are then guided by ML combined with grid searching to co-optimize device performance, including mobility, threshold voltage and subthreshold swing. A 62-level SPICE modeling was implemented for MoS 2 FETs and further used to construct functional digital, analog, and photodetection circuits. Finally, we present wafer-scale test FET arrays and a 4-bit full adder employing industry-standard design flows and processes. Taken together, these results experimentally validate the application potential of ML-assisted fabrication optimization for beyond-silicon electronic materials. Here, the authors demonstrate the application of machine learning to optimize the device fabrication process for wafer-scale 2D semiconductors, and eventually fabricate digital, analog, and optoelectrical circuits.