Low-thermal-budget synthesis of monolayer molybdenum disulfide for silicon back-end-of-line integration on a 200 mm platform

• Published in: Nature nanotechnology Vol. 18; no. 5; pp. 456 - 463
• Main Authors: Zhu, Jiadi, Park, Ji-Hoon, Vitale, Steven A., Ge, Wenjun, Jung, Gang Seob, Wang, Jiangtao, Mohamed, Mohamed, Zhang, Tianyi, Ashok, Maitreyi, Xue, Mantian, Zheng, Xudong, Wang, Zhien, Hansryd, Jonas, Chandrakasan, Anantha P., Kong, Jing, Palacios, Tomás
• Format: Journal Article
• Language: English
• Published: London Nature Publishing Group UK 01.05.2023; Nature Publishing Group
• Subjects: 140/133; 142/126; 639/166/987; 639/301/1005/1007; 639/925/357/995; Budgets; Chemical synthesis; Chemistry and Materials Science; Circuit design; Circuits; CMOS; Contamination; Decomposition; Diameters; electrical engineering; Electron mobility; electronic devices; electronic engineering; electronic materials; electronic properties; Electronics; Fabrication; Foundries; High temperature; Integration; Low temperature; Materials Science; Metalorganic chemical vapor deposition; Molybdenum; Molybdenum disulfide; Monolayers; NANOSCIENCE AND NANOTECHNOLOGY; Nanotechnology; Nanotechnology and Microengineering; Organic chemicals; Organic chemistry; Precursors; Silicon; Silicon devices; Temperature requirements; Threshold voltage; Transistors; Two dimensional materials; Wafers
• ISSN: 1748-3387; 1748-3395; 1748-3395
• DOI: 10.1038/s41565-023-01375-6

Two-dimensional (2D) materials are promising candidates for future electronics due to their excellent electrical and photonic properties. Although promising results on the wafer-scale synthesis (≤150 mm diameter) of monolayer molybdenum disulfide (MoS 2 ) have already been reported, the high-quality synthesis of 2D materials on wafers of 200 mm or larger, which are typically used in commercial silicon foundries, remains difficult. The back-end-of-line (BEOL) integration of directly grown 2D materials on silicon complementary metal–oxide–semiconductor (CMOS) circuits is also unavailable due to the high thermal budget required, which far exceeds the limits of silicon BEOL integration (<400 °C). This high temperature forces the use of challenging transfer processes, which tend to introduce defects and contamination to both the 2D materials and the BEOL circuits. Here we report a low-thermal-budget synthesis method (growth temperature < 300 °C, growth time ≤ 60 min) for monolayer MoS 2 films, which enables the 2D material to be synthesized at a temperature below the precursor decomposition temperature and grown directly on silicon CMOS circuits without requiring any transfer process. We designed a metal–organic chemical vapour deposition reactor to separate the low-temperature growth region from the high-temperature chalcogenide-precursor-decomposition region. We obtain monolayer MoS 2 with electrical uniformity on 200 mm wafers, as well as a high material quality with an electron mobility of ~35.9 cm 2  V −1  s −1 . Finally, we demonstrate a silicon-CMOS-compatible BEOL fabrication process flow for MoS 2 transistors; the performance of these silicon devices shows negligible degradation (current variation < 0.5%, threshold voltage shift < 20 mV). We believe that this is an important step towards monolithic 3D integration for future electronics. Monolayer MoS 2 is grown at the back end of the line of 200 mm silicon CMOS wafers at a temperature of <300 °C, and hybrid silicon CMOS/MoS 2 circuits are demonstrated through heterogeneous integration.