Pseudo-Static Gain Cell of Embedded DRAM for Processing-in-Memory in Intelligent IoT Sensor Nodes

• Published in: Sensors (Basel, Switzerland) Vol. 22; no. 11; p. 4284
• Main Authors: Kim, Subin, Park, Jun-Eun
• Format: Journal Article
• Language: English
• Published: Switzerland MDPI AG 04.06.2022; MDPI
• Subjects: Access time; Circuit design; Data integrity; Design and construction; Dynamic cell; Dynamic random access memory; Electric potential; gain-cell embedded DRAM (eDRAM); Internet of Things; Layouts; Leakage current; Methods; Monte Carlo simulation; Operating temperature; processing-in-memory (PIM); pseudo-static leakage compensation (PSLC); Retention; Transistors; Voltage; South Korea; pseudo-static leakage compensation (PSLC); processing-in-memory (PIM); gain-cell embedded DRAM (eDRAM)
• ISSN: 1424-8220; 1424-8220
• DOI: 10.3390/s22114284

This paper presents a pseudo-static gain cell (PS-GC) with extended retention time for an embedded dynamic random-access memory (eDRAM) macro for analog processing-in-memory (PIM). The proposed eDRAM cell consists of a two-transistor (2T) gain cell with a pseudo-static leakage compensation that maintains stored data without charge loss issue. Hence, the PS-GC can offer unlimited retention time in the same manner as static RAM (SRAM). Due to the extended retention time, bulky capacitors in conventional eDRAM are no longer needed, thereby, improving the area efficiency of eDRAM-based analog PIMs. The active leakage compensation of the PS-GC can effectively hold stored data even in a deep-submicron process that show significant leakage current. Therefore, the PS-GC can accelerate write-access time and read-access time without concern of increased leakage current. The proposed gain cell and its 64 × 64 eDRAM macro were implemented in a 28 nm CMOS process. The bitcell of the proposed gain cell has 0.79- and 0.58-times the area of those of 6T SRAM and 8T STAM, respectively. The post-layout simulation results demonstrate that the eDRAM maintains the pseudo-static operation with unlimited retention time successfully under wide range variations of process, voltage and temperature. At the operating frequency of 667 MHz, the eDRAM macro achieved an operating voltage range from 0.9 to 1.2 V and operating temperature range from -25 to 85 °C regardless of the process variation. The post-layout simulated write-access time and read-access time were below 0.3 ns at an operating temperature of 85 °C. The PS-GC consumes a static power of 2.2 nW/bit at an operating temperature of 25 °C.