Delamination and solder flow-out in underfilled and Pb-free flip chips on laminate

• Published in: Microelectronics international Vol. 22; no. 2; pp. 28 - 34
• Main Authors: van Kleef, Marc, Bielen, Jeroen, Gülpen, Jan, Ramos, Mike
• Format: Journal Article
• Language: English
• Published: Bradford Emerald Group Publishing Limited 01.08.2005; MCB University Press
• Subjects: Applied sciences; Design of experiments; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Failure; Failure analysis; Finite element analysis; Integrated circuits; Metal fatigue; Microelectronics; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Simulation; Soldering; Studies; Trends; Solder; Laminates; Moisture measurement; LGA technology; Numerical method; Hybrid system; Finite element method; Integrated circuit bonding; Electronic packaging; Delamination; Flip chip bonding; Fatigue life; Die; Stratified material; Flip-chip; Durability; Solder metal; Failures; Mismatching; Thermal expansion; Humidity effect; Solder bump; Mechanical stress; Experimental design; Soldered joint; Lead free soldering; Reliability; Reflow soldering; Via hole
• ISSN: 1356-5362; 1758-812X
• DOI: 10.1108/13565360510593710

Purpose - In land grid array hybrid or system in package type products passive integration on silicon dies are flip chip mounted on a laminate substrate using Pb-free solder. To increase the solder bump fatigue life, underfill is applied. The application of underfill resulted in the occurrence of an unexpected and unwanted phenomenon: solder flowing out of the underfill during a second level reflow test. The occurrence of solder flow-out seemed associated with moisturizing as part of a moisture sensitivity level assessment. The solder flow-out is preceded by delamination, initiated by mismatch in coefficient of thermal expansion between copper through-holes and laminate. This paper aims to describe the phenomenon and possible solutions by combining experiments with finite element (FE) simulations.Design methodology approach - Ways to prevent this kind of overstress failures are investigated by design of experiments and observed trends are compared with thermo-mechanical FE simulations. A significant contribution is made by through-holes close to the bump and underfill fillet.Findings - The FE simulations confirmed increased thermo-mechanical induced stress levels by bad positioning of vias, underfill and solder. The integrity of the flip chip construction is substantially improved by optimising product design, underfill material and the associated assembly process.Originality value - This paper is a useful source of information on the causes of delamination and solder flow-out.