Hardware stream cipher with controllable chaos generator for colour image encryption

• Published in: IET image processing Vol. 8; no. 1; pp. 33 - 43
• Main Authors: Barakat, Mohamed L, Mansingka, Abhinav S, Radwan, Ahmed G, Salama, Khaled N
• Format: Journal Article
• Language: English
• Published: Stevenage The Institution of Engineering and Technology 01.01.2014; Institution of Engineering and Technology; The Institution of Engineering & Technology
• Subjects: Applied sciences; bit permutations; Chaos theory; chaotic sequence; colour image encryption; controllable chaos generator; Cryptography; Encryption; Exact sciences and technology; Field programmable gate arrays; Hardware; hardware stream cipher; image colour analysis; Image processing; Information, signal and communications theory; Security; Signal and communications theory; Streams; Telecommunications and information theory; Xilinx Virtex 4 FPGA; XORing; chaotic sequence; hardware stream cipher; field programmable gate arrays; bit permutations; cryptography; image colour analysis; XORing; controllable chaos generator; Xilinx Virtex 4 FPGA; colour image encryption; Chaos; Performance evaluation; Stream ciphering; Chaos generators; Third order; Information rate; Field programmable gate array; Non linear phenomenon; Information transmission; Color image; Implementation; Private key; Security of data; Non linear effect; Chaotic systems; High rate transmission
• ISSN: 1751-9659; 1751-9667; 1751-9667
• DOI: 10.1049/iet-ipr.2012.0586

This study presents hardware realisation of chaos-based stream cipher utilised for image encryption applications. A third-order chaotic system with signum non-linearity is implemented and a new post processing technique is proposed to eliminate the bias from the original chaotic sequence. The proposed stream cipher utilises the processed chaotic output to mask and diffuse input pixels through several stages of XORing and bit permutations. The performance of the cipher is tested with several input images and compared with previously reported systems showing superior security and higher hardware efficiency. The system is experimentally verified on XilinxVirtex 4 field programmable gate array (FPGA) achieving small area utilisation and a throughput of 3.62 Gb/s.