Magnetic Skyrmion as a Spintronic Deep Learning Spiking Neuron Processor

• Published in: IEEE transactions on magnetics Vol. 54; no. 8; pp. 1 - 7
• Main Authors: Chen, Mei-Chin, Sengupta, Abhronil, Roy, Kaushik
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.08.2018; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Biological neural networks; Circuit design; CMOS; Co-design; Computer architecture; Computer simulation; Deep learning; Deep learning architectures; Digits; Energy consumption; Feasibility studies; Handwriting; Handwriting recognition; Hardware; Hypothetical particles; magnetic Skyrmion (MS); Magnetic tunneling; Magnetism; magnus force; Micromagnetics; Microprocessors; Neural networks; Neurons; Particle theory; Pattern recognition; Semiconductor devices; Spiking; spiking neural network (SNN); Spintronics; Synapses; Task complexity; Transistors
• ISSN: 0018-9464; 1941-0069
• DOI: 10.1109/TMAG.2018.2845890

Deep spiking neural networks (SNNs) have emerged as one of the popular architectures in complex pattern recognition and classification tasks that can be enabled by low-power neuromorphic hardware. However, hardware implementation of such algorithms using conventional CMOS devices is area expensive and energy inefficient. This is owing to the fundamental mismatch between the underlying neuromophic computations and the CMOS transistors along with energy consumption involved in synaptic memory-access operations. Hence, there is a need for novel "neuro-mimetic" devices offering a direct mapping to synaptic and neuronal functionalities together with the possibility of providing in situ synaptic storage. Magnetic skyrmions have recently been proposed as a promising alternative for next-generation information carrier due to remarkably high stability, ultra-low depinning current density, and extremely compact size. In this paper, the design of skyrmion-based devices to emulate biological synapses and neurons is explored, and skyrmionic synapse-based crossbar architectures driving skyrmionic neurons are proposed. We perform a systematic device-circuit-architecture co-design for digit recognition with the MNIST handwritten digits dataset to evaluate the feasibility of our proposal. The device-to-system simulations indicate that the proposed skyrmion-based devices in deep SNNs can potentially achieve two orders of magnitude improvement in energy consumption over an optimized CMOS implementation at a 45 nm technology node.