Adaptive Proactive Reconfiguration: A Technique for Process-Variability- and Aging-Aware SRAM Cache Design

• Published in: IEEE transactions on very large scale integration (VLSI) systems Vol. 23; no. 9; pp. 1951 - 1955
• Main Authors: Pouyan, Peyman, Amat, Esteve, Rubio, Antonio
• Format: Journal Article Publication
• Language: English
• Published: IEEE 01.09.2015
• Subjects: Adaptive proactive reconfiguration; Aging; aging sensor; Circuits electrònics; Enginyeria electrònica; Memòria d'accés aleatori; Microelectrònica; Monitoring; process variation; Random access memory; reliability; SRAM cells; static random access memory (SRAM); Temperature measurement; Transistors; Very large scale integration; Àrees temàtiques de la UPC; Adaptive proactive reconfiguration; static random access memory (SRAM); aging sensor; process variation; reliability
• ISSN: 1063-8210; 1557-9999
• DOI: 10.1109/TVLSI.2014.2355873

Nanoscale circuits are subject to a wide range of new limiting phenomena making essential to investigate new design strategies at the circuit and architecture level to improve its performance and reliability. Proactive reconfiguration is an emerging technique oriented to extend the system lifetime of memories affected by aging. In this brief, we present a new approach for static random access memory (SRAM) design that extends the cache lifetime when considering process variation and aging in the memory cells using an adaptive strategy. To track the aging in the SRAM cells we propose an on-chip monitoring technique. Our results show the technique as a feasible way to extend the cache lifetime up to 5X.