Controlling chaos using edge computing hardware

Machine learning provides a data-driven approach for creating a digital twin of a system – a digital model used to predict the system behavior. Having an accurate digital twin can drive many applications, such as controlling autonomous systems. Often, the size, weight, and power consumption of the d...

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Bibliographic Details
Published inNature communications Vol. 15; no. 1; p. 3886
Main Authors Kent, Robert M., Barbosa, Wendson A. S., Gauthier, Daniel J.
Format Journal Article
LanguageEnglish
Published London Nature Publishing Group UK 08.05.2024
Nature Publishing Group
Nature Portfolio
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Summary:Machine learning provides a data-driven approach for creating a digital twin of a system – a digital model used to predict the system behavior. Having an accurate digital twin can drive many applications, such as controlling autonomous systems. Often, the size, weight, and power consumption of the digital twin or related controller must be minimized, ideally realized on embedded computing hardware that can operate without a cloud-computing connection. Here, we show that a nonlinear controller based on next-generation reservoir computing can tackle a difficult control problem: controlling a chaotic system to an arbitrary time-dependent state. The model is accurate, yet it is small enough to be evaluated on a field-programmable gate array typically found in embedded devices. Furthermore, the model only requires 25.0 ± 7.0 nJ per evaluation, well below other algorithms, even without systematic power optimization. Our work represents the first step in deploying efficient machine learning algorithms to the computing “edge.” Creating accurate digital twins and controlling nonlinear systems displaying chaotic dynamics is challenging due to high system sensitivity to initial conditions and perturbations. The authors introduce a nonlinear controller for chaotic systems, based on next-generation reservoir computing, with improved accuracy, energy cost, and suitable for implementation with field-programmable gate arrays.
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ISSN:2041-1723
2041-1723
DOI:10.1038/s41467-024-48133-3