Pipelining a Multi-Mode SHA-384/512 Core with High Area Performance Rate

• Published in: IEICE Transactions on Information and Systems Vol. E92.D; no. 10; pp. 2034 - 2042
• Main Authors: HOANG, Anh-Tuan, YAMAZAKI, Katsuhiro, OYANAGI, Shigeru
• Format: Journal Article
• Language: English
• Published: Oxford The Institute of Electronics, Information and Communication Engineers 2009; Oxford University Press
• Subjects: Applied sciences; Balancing; Circuit properties; Computation; Cryptography; Design. Technologies. Operation analysis. Testing; Digital circuits; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Exact sciences and technology; fine-grained pipelining; FPGA; Hardware; Information, signal and communications theory; Integrated circuits; Iterative methods; Messages; Pipelines; Pipelining (computers); Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; SHA-2; Signal and communications theory; Similarity; Systems, networks and services of telecommunications; Telecommunications; Telecommunications and information theory; Transmission and modulation (techniques and equipments); Performance evaluation; High performance; Arithmetic circuit; Multistage method; SHA-2; Similarity; FPGA; Information rate; Iterative method; Routing; Field programmable gate array; Algorithm; Information transmission; Implementation; Pipeline processing; fine-grained pipelining; Granular material; Summing circuits; Integrated circuit; Security of data; Critical path; Delay time; Cryptography; Multistage circuit
• ISSN: 0916-8532; 1745-1361; 1745-1361
• DOI: 10.1587/transinf.E92.D.2034

The security hash algorithm 512 (SHA-512), which is used to verify the integrity of a message, involves computational iterations on data. The huge computation delay generated in such iterations limits the entire throughput of the system and makes it difficult to pipeline the computation. We describe a way to pipeline the computation using fine-grained pipelining with balanced critical paths. In this method, one critical path is broken into two stages by using data forwarding. The other critical path is broken into three stages by using computation postponement. The resulting critical paths all have two adder-layers with some data movements, and thus are balanced. In addition, the method also allows register reduction. Also, the similarity in SHA-384 and SHA-512 are used for a multi-mode design, which can generate a message digest for both versions with the same throughput, but with only a small increase in hardware size. Experimental results show that our implementation achieved not only the best area performance rate (throughput divided by area), but also a higher throughput than almost all related work.