A 256 mW 40 Mbps Full-HD H.264 High-Profile Codec Featuring a Dual-Macroblock Pipeline Architecture in 65 nm CMOS

• Published in: IEEE journal of solid-state circuits Vol. 44; no. 4; pp. 1184 - 1191
• Main Authors: Iwata, K., Mochizuki, S., Kimura, M., Shibayama, T., Izuhara, F., Ueda, H., Hosogi, K., Nakata, H., Ehama, M., Kengaku, T., Nakazawa, T., Watanabe, H.
• Format: Journal Article Conference Proceeding
• Language: English
• Published: New York, NY IEEE 01.04.2009; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Circuit properties; Circuits; CMOS; Code standards; Codec; Consumption; Design. Technologies. Operation analysis. Testing; Electric, optical and optoelectronic circuits; Electronic circuits; Electronics; Energy consumption; Exact sciences and technology; Extensibility; Frequency; full HD; H.264; High definition video; Image coding; Integrated circuits; Integrated circuits by function (including memories and processors); low power consumption; mobile applications; multiple video standard; Pipelines; Real time; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Signal convertors; Streaming media; video codec; Video codecs; Video coding; video codec; Processor; Scalability; H.264; low power consumption; full HD; Pipeline processing; Codec; Power consumption; Operating rate; Coding; Complementary MOS technology; Integrated circuit; mobile applications; Low-power electronics; Custom circuit; multiple video standard
• ISSN: 0018-9200; 1558-173X
• DOI: 10.1109/JSSC.2009.2014025

A video-size-scalable H.264 high-profile codec including 19 application-specific CPUs for extensibility to multiple standards has been fabricated in 65 nm CMOS. With two parallel pipelines for macroblock processing, the codec consumed 256 mW in real-time encoding of 40 Mbp full-HDs (1080p30) video at an operating frequency of 162 MHz.