Investigation on Self-Heating Effect in Gate-All-Around Silicon Nanowire MOSFETs From Top-Down Approach

• Published in: IEEE electron device letters Vol. 30; no. 5; pp. 559 - 561
• Main Authors: Wang, Runsheng, Zhuge, Jing, Huang, Ru, Kim, Dong-Won, Park, Donggun, Wang, Yangyuan
• Format: Journal Article
• Language: English
• Published: New York, NY IEEE 01.05.2009; Institute of Electrical and Electronics Engineers; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Applied sciences; Automatic testing; Circuits; CMOS technology; Design. Technologies. Operation analysis. Testing; Devices; Dielectric substrates; Electronics; Exact sciences and technology; Gate-all-around (GAA); Germanium silicon alloys; Integrated circuits; MOSFETs; Nanocomposites; Nanomaterials; Nanoscale devices; Nanostructure; Nanowires; Scattering; self-heating effect; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicon; Silicon germanium; silicon nanowire MOSFET (SNWT); Silicon substrates; Testing, measurement, noise and reliability; Thermal conductivity; Transistors; MOSFET; Thermal behavior; GAA transistor; Multiconductor line; Silicon on insulator technology; Complementary MOS technology; silicon nanowire MOSFET (SNWT); Gate-all-around (GAA); Testing equipment; Self heating; Miniaturization; Nanowires; Phonon scattering; self-heating effect
• ISSN: 0741-3106; 1558-0563
• DOI: 10.1109/LED.2009.2016764

The self-heating effect is becoming a critical concern for nanoscaled devices with low dimensions. In this letter, the self-heating effect is experimentally investigated in gate-all-around (GAA) silicon nanowire MOSFETs (SNWTs) fabricated from the CMOS-compatible top-down approach. With the multifinger and multiwire test structure, the impact of the self-heating effect is successfully characterized. The results indicate that even if the SNWT is fabricated on the bulk silicon substrate, the impact of the self-heating effect is comparable or even a little bit worse than that in SOI devices, probably due to the 1-D nature of nanowire and increased phonon-boundary scattering in the GAA architecture.