A General Space Vector PWM Algorithm for Multilevel Inverters, Including Operation in Overmodulation Range

This paper proposes a simple space vector pulsewidth modulation algorithm for a multilevel inverter for operation in the overmodulation range. The proposed scheme easily determines the location of the reference vector and calculates on-times. It uses a simple mapping to generate gating signals for t...

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Bibliographic Details
Published inIEEE transactions on power electronics Vol. 22; no. 2; pp. 517 - 526
Main Authors Gupta, A.K., Khambadkone, A.M.
Format Journal Article
LanguageEnglish
Published New York, NY IEEE 01.03.2007
Institute of Electrical and Electronics Engineers
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects
Algebra
Algorithms
Applied sciences
Capacitors
Cascaded H-bridge inverter
Circuit properties
Control systems
Digital signal processing
Electric currents
Electric power
Electric, optical and optoelectronic circuits
Electrical engineering. Electrical power engineering
Electronic circuits
Electronic equipment and fabrication. Passive components, printed wiring boards, connectics
Electronics
Exact sciences and technology
Gating and risering
Inverters
Mathematical analysis
Modulation
modulation index
Multilevel
multilevel inverter
overmodulation
Power electronics, power supplies
Power generation
Pulse duration modulation
Pulse inverters
Pulse width modulation inverters
Signal convertors
Signal mapping
Space vector pulse width modulation
space vector pulsewidth modulation (SVPWM)
Topology
Vectors (mathematics)
Voltage control
Inverter
Power converter
Cascaded H-bridge inverter
Power electronics
Mapping
Experimental study
Overmodulation
Algorithm
multilevel inverter
Vector space
Neutral point connection
modulation index
space vector pulsewidth modulation (SVPWM)
Pulse duration modulation
Multilevel system
Cascade connection
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Summary:This paper proposes a simple space vector pulsewidth modulation algorithm for a multilevel inverter for operation in the overmodulation range. The proposed scheme easily determines the location of the reference vector and calculates on-times. It uses a simple mapping to generate gating signals for the inverter. A five-level cascaded inverter is used to explain the scheme. The scheme can be easily extended to a n-level inverter. It is applicable to neutral point clamped topology as well. Experimental results are provided for five-level and seven-level cascaded inverters
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0885-8993
1941-0107
DOI:10.1109/TPEL.2006.889937