Design considerations of high voltage RESURF nLDMOS: An analytical and numerical study
In this paper, a RESURF high voltage (HV) nLDMOS is designed in 0.35μm BiCMOS technology (STMicroelectronics technology-like). Optimization of the key device/process parameters of the device is performed using analytical approach and verified using advanced 2D numerical simulation. The results show...
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Published in | Ain Shams Engineering Journal Vol. 6; no. 2; pp. 501 - 509 |
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Main Authors | , , , , |
Format | Journal Article |
Language | English |
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Elsevier B.V
01.06.2015
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Abstract | In this paper, a RESURF high voltage (HV) nLDMOS is designed in 0.35μm BiCMOS technology (STMicroelectronics technology-like). Optimization of the key device/process parameters of the device is performed using analytical approach and verified using advanced 2D numerical simulation. The results show excellent RON,SP/BV trade-off (BV≈400V and RON,SP=9.5mΩcm2 for Tepi=4μm and LDrift=17μm) without any added process complexity. The maximum obtained drain current is 1.8mA/μm at a gate voltage of 5V. The designed device is suitable for smart power integration. |
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AbstractList | In this paper, a RESURF high voltage (HV) nLDMOS is designed in 0.35 μm BiCMOS technology (STMicroelectronics technology-like). Optimization of the key device/process parameters of the device is performed using analytical approach and verified using advanced 2D numerical simulation. The results show excellent RON,SP/BV trade-off (BV ≈ 400 V and RON,SP = 9.5 mΩ cm2 for Tepi = 4 μm and LDrift = 17 μm) without any added process complexity. The maximum obtained drain current is 1.8 mA/μm at a gate voltage of 5 V. The designed device is suitable for smart power integration. In this paper, a RESURF high voltage (HV) nLDMOS is designed in 0.35μm BiCMOS technology (STMicroelectronics technology-like). Optimization of the key device/process parameters of the device is performed using analytical approach and verified using advanced 2D numerical simulation. The results show excellent RON,SP/BV trade-off (BV≈400V and RON,SP=9.5mΩcm2 for Tepi=4μm and LDrift=17μm) without any added process complexity. The maximum obtained drain current is 1.8mA/μm at a gate voltage of 5V. The designed device is suitable for smart power integration. |
Author | Abouelatta-Ebrahim, Mohamed Zekry, Abdelhalim Gontrand, Christian Shaker, Ahmed Sayah, Gihan T. |
Author_xml | – sequence: 1 givenname: Mohamed surname: Abouelatta-Ebrahim fullname: Abouelatta-Ebrahim, Mohamed email: m.abouelatta@eng.asu.edu.eg organization: Faculty of Engineering, Ain Shams University, Cairo, Egypt – sequence: 2 givenname: Ahmed surname: Shaker fullname: Shaker, Ahmed email: ahmed.shaker@eng.asu.edu.eg, ashaker2k@yahoo.com organization: Faculty of Engineering, Ain Shams University, Cairo, Egypt – sequence: 3 givenname: Gihan T. surname: Sayah fullname: Sayah, Gihan T. email: gtsayah@hotmail.com organization: Nuclear Materials Authority, Cairo, Egypt – sequence: 4 givenname: Christian surname: Gontrand fullname: Gontrand, Christian email: Christian.Gontrand@insa-lyon.fr organization: Université de Lyon, Institut des Nanotechnologies de Lyon INL-UMR5270, CNRS, INSA de Lyon, Villeurbanne F-69621, France – sequence: 5 givenname: Abdelhalim surname: Zekry fullname: Zekry, Abdelhalim email: aaazekry@hotmail.com organization: Faculty of Engineering, Ain Shams University, Cairo, Egypt |
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CitedBy_id | crossref_primary_10_1016_j_mejo_2023_105911 crossref_primary_10_4028_www_scientific_net_MSF_1004_830 crossref_primary_10_1109_TED_2020_3019479 crossref_primary_10_1109_TED_2021_3131922 crossref_primary_10_1007_s40009_019_00830_0 crossref_primary_10_1007_s42341_024_00530_7 |
Cites_doi | 10.1016/S0026-2692(00)00012-4 10.1109/16.47787 10.1109/TED.2004.835163 10.1109/ISIE.2010.5637652 10.1051/epjap/2011100138 10.1109/5.931471 10.1109/TED.2003.821383 |
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Keywords | Smart power integrated circuit (SPIC) Specific ON-resistance Breakdown voltage RESURF 0.35μm BiCMOS nLDMOS |
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Snippet | In this paper, a RESURF high voltage (HV) nLDMOS is designed in 0.35μm BiCMOS technology (STMicroelectronics technology-like). Optimization of the key... In this paper, a RESURF high voltage (HV) nLDMOS is designed in 0.35 μm BiCMOS technology (STMicroelectronics technology-like). Optimization of the key... |
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SubjectTerms | 0.35 μm BiCMOS 0.35 μm BiCMOS Breakdown voltage nLDMOS RESURF Smart power integrated circuit (SPIC) Specific ON-resistance |
Title | Design considerations of high voltage RESURF nLDMOS: An analytical and numerical study |
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